1. Field of the Invention
In this specification, a semiconductor device provided with a nonvolatile memory element capable of writing and erasing information will be described.
2. Description of the Related Art
A nonvolatile semiconductor memory device is a semiconductor device provided with a nonvolatile memory element capable of writing and erasing information, and is utilized as recording media of various electronic devices such as digital still cameras, portable audio players, and cellular phones. As typical nonvolatile semiconductor memory devices, EEPROM (Electrically Erasable and Programmable Read Only Memory) and a flash memory can be given.
Since electric charges of Fowler-Nordheim (F-N) tunneling current, a hot electron, and the like are used for rewriting a nonvolatile memory element which is applied to a nonvolatile semiconductor memory device, a tunnel insulating film of the nonvolatile memory element or an interface thereof deteriorates by repetition of rewriting. Therefore, theoretically, the rewritable number of the nonvolatile memory element has limitation. A variety of technologies have been developed regarding how to improve rewriting endurance of the nonvolatile memory element and as to an insulating film, an element structure, a rewriting method, and the like (for example, see Patent Documents 1 and 2).
In addition, in operational principle, a high driving voltage (a writing voltage and an erasing voltage) is necessary for rewriting of a nonvolatile memory element. Therefore, the nonvolatile semiconductor memory device is provided with a voltage generation circuit that generates a writing voltage and an erasing voltage and a circuit that needs a transistor which can withstand a high driving voltage. Thus, a plurality of semiconductor elements each having a different structure, such as a nonvolatile memory element, a transistor that can withstand a high driving voltage (hereinafter referred to as the “high withstand voltage transistor”), and a transistor applied to a circuit where high-speed operation is required, need to be manufactured at the same time using one substrate. For example, in Patent Document 3, it is described that a transistor having a thin gate insulating film and a transistor having a thick gate insulating film are manufactured at the same time over one substrate together with a nonvolatile memory element. In Patent Document 3, the transistor having a thin gate insulating film is applied to a transistor where a driving voltage is low and variation in a threshold voltage is desired to be suppressed, whereas the transistor having a thick gate insulating film is applied to a high withstand voltage transistor.
An example of a structure of the nonvolatile memory element disclosed in Patent Document 3 will be described below with reference to FIGS. 14A and 14B. FIGS. 14A and 14B are each a cross-sectional view of a nonvolatile memory element 910 disclosed in Patent Document 3. FIG. 14A is a cross-sectional view taken along a channel length direction (in a direction perpendicular to a gate), and FIG. 14B is a cross-sectional view taken along a channel width direction (in a direction horizontal to the gate).
As illustrated in FIGS. 14A and 14B, the nonvolatile memory element 910 (hereinafter referred to as the “memory element 910”) is provided over a glass substrate 900 with an insulating film 901 interposed therebetween. The glass substrate 900 is used as a substrate having an insulating surface. The memory element 910 includes an island-like semiconductor region 911 over the insulating film 901, and a floating gate electrode 913 and a control gate electrode 914 over the island-like semiconductor region 911.
The island-like semiconductor region 911 is provided with a channel formation region 915, a source region 916, a drain region 917, and LDD regions 918 and 919. An insulating film 902 is provided over the island-like semiconductor region 911, and the floating gate electrode 913 is provided over the island-like semiconductor region 911 with the insulating film 902 interposed therebetween. In addition, the control gate electrode 914 is provided over the floating gate electrode 913 with an insulating film 903 interposed therebetween. The insulating film 902 forms a gate insulating film between the island-like semiconductor region 911 and the floating gate electrode 913, and the insulating film 903 forms a gate insulating film between the floating gate electrode 913 and the control gate electrode 914. In this specification, in a nonvolatile memory element, the former gate insulating film is referred to as a first gate insulating film, and the latter gate insulating film is referred to as a second gate insulating film.
An insulating film 904 is provided so as to cover the island-like semiconductor region 911, the floating gate electrode 913, and the control gate electrode 914. A wiring 921, a wiring 922, and a wiring 923 are formed over the insulating film 904 and are electrically connected to the source region 916 and the drain region 917 of the island-like semiconductor region 911, and the control gate electrode 914, respectively, through contact holes.
Next, an example of a method for manufacturing a nonvolatile semiconductor memory device which is disclosed in Patent Document 3 will be described with reference to FIGS. 15A to 15C, FIGS. 16A and 16B, FIGS. 17A and 17B, and FIGS. 18A and 18B. Here, a method for manufacturing an n-channel transistor 930 and a p-channel transistor 950 over the glass substrate 900 is described together with the memory element 910 illustrated in FIGS. 14A and 14B. Here, the transistors 930 and 950 are manufactured as transistors having a high withstand voltage. FIGS. 15A to 15C, FIGS. 16A and 16B, and FIGS. 17A and 17B are cross-sectional views which illustrate an example of a method for manufacturing the memory element 910, the n-channel transistor 930, and the p-channel transistor 950. Note that FIGS. 15A to 15C, FIGS. 16A and 16B, and FIGS. 17A and 17B are cross-sectional views of each element in a channel length direction, and the memory element 910, the n-channel transistor 930 (hereinafter referred to as the “transistor 930”), and the p-channel transistor 950 (hereinafter referred to as the “transistor 950”) are illustrated in line A-B, line C-D, and line E-F, respectively. In addition, FIGS. 18A and 18B are cross-sectional views of each element in a channel width direction, and the memory element 910, the transistor 930, and the transistor 950 are illustrated in line G-H, line I-J, and line K-L, respectively.
As illustrated in FIG. 15A and FIG. 18A, the insulating film 901 is formed over the glass substrate 900. The island-like semiconductor region 911, an island-like semiconductor region 931, and an island-like semiconductor region 951 which each include a silicon film are formed over the insulating film 901. The insulating film 902 and a conductive film 981 are stacked over these regions (911, 931, and 951).
Next, as illustrated in FIG. 15B, the conductive film 981 is processed into a desired shape, so that the floating gate electrode 913 is formed over the island-like semiconductor region 911 with the insulating film 902 interposed therebetween. Next, the insulating film 902 is removed from the region where the transistors 930 and 950 are to be formed. The insulating film 902 which exists between the island-like semiconductor region 911 and the floating gate electrode 913 forms the first gate insulating film.
Next, as illustrated in FIG. 15C, an n-type impurity element is added to form LDD (Lightly Doped Drain) regions in the island-like semiconductor regions 911 and 931. This addition of an impurity element is performed after a resist which covers the island-like semiconductor region 951 is formed by a photolithography step. Through this step of adding an impurity element, n-type low concentration impurity regions 982 to 985 are formed in the island-like semiconductor regions 911 and 931. Next, the insulating film 903 is formed so as to cover the island-like semiconductor regions 911, 931, and 951. This insulating film 903 forms the second gate insulating film between the floating gate electrode 913 and the control gate electrode 914 in the memory element 910 and forms gate insulating films in the transistors 930 and 950. Therefore, it is preferable to provide the insulating film 903 as an insulating film thicker than the insulating film 902 so that the transistors 930 and 950 have a dielectric strength voltage with respect to a high driving voltage.
Next, a conductive film is formed over the insulating film 903. This conductive film is processed into a desired shape, so that the control gate electrode 914 of the memory element 910 and a gate electrode 934 of the transistor 930 and a gate electrode 954 of the transistor 950 are formed (see FIG. 16A).
Next, as illustrated in FIG. 16B, a photolithography step is performed to form a resist 986 which covers the island-like semiconductor region 951. Then, an n-type impurity element is added to the island-like semiconductor regions 911 and 931 using the control gate electrode 914 and the gate electrode 934 as masks. Through this step, the channel formation region 915, the source region 916, the drain region 917, and the LDD regions 918 and 919 are formed in the island-like semiconductor region 911; and a channel formation region 935, a source region 936, a drain region 937, and LDD regions 938 and 939 are formed in the island-like semiconductor region 931.
Then, as illustrated in FIG. 17A, a resist 987 which covers the island-like semiconductor regions 911 and 931 is formed by a photolithography step. Next, a p-type impurity element is added to the island-like semiconductor region 951 using the gate electrode 954 as a mask. Through this step, a channel formation region 955, a source region 956, and a drain region 957 are formed in the island-like semiconductor region 951 in a self-aligned manner.
Next, as illustrated in FIG. 17B and FIG. 18B, the insulating film 904 is formed to form a plurality of contact holes in the insulating films 904, 903, and 902. Then, a conductive film is formed over the insulating film 904 and processed into a desired shape. Accordingly, the wirings 921 to 923 electrically connected to the memory element 910, wirings 941 to 943 electrically connected to the transistor 930, and wirings 961 to 963 electrically connected to the transistor 950 are formed. Through the above-described steps, the memory element 910, the transistor 930, and the transistor 950 are completed (see FIG. 17B and FIG. 18B).
As illustrated in FIG. 17B and FIG. 18B, the second gate insulating film of the memory element 910 and the gate insulating films of the transistors 930 and 950 are formed using the common insulating film 903. It is preferable to provide the insulating film 903 with a film thickness thick enough to withstand a high driving voltage so that the transistors 930 and 950 each have a structure suitable for a high withstand voltage transistor. On the other hand, since the insulating film 903 serves as the second gate insulating film between the floating gate electrode 913 and the control gate electrode 914, a rewriting voltage of the memory element 910 increases when the film thickness of the insulating film 903 is increased. In addition, rewriting endurance of the memory element 910 is easily affected by dielectric strength characteristics of the insulating film 903 and an interface state between the island-like semiconductor region 911 and the insulating film 903.